In the communications field, there is a constant need to transmit larger amounts of digital data in shorter time intervals. In accordance with one method that is gaining increasing acceptance, data is transmitted over high-speed serial buses. These buses often carry digital data serially over a pair of conductors, driven either in a single-ended form or differentially. The differential drive method offers advantages over the single-ended drive method. The noise immunity of the differential method is greater than that of a comparable single-ended method. The improved noise immunity allows the use of lower signal amplitudes on the differential bus compared to the single-ended bus. Lower signal amplitudes often enable higher data transmission rates and lower overall power consumption.
One conventional standard for differential data transmission is referred to as the low voltage differential signaling (LVDS) standard, defined in “TIA/EIA-644, revision A, Electrical Characteristic of Low Voltage Differential Signaling (LVDS) Interface Circuits” and “ANSI/TIA/EIA-644, revision A, Jan. 30, 2001” published by Telecommunications Industry Association. This standard defines a differential data bus with a recommended maximum data signaling rate of 655 million bits per second on up to 5 meters of wire cable. The standard also requires that the generator, or transmitter, be able to generate a differential voltage signal in the range of 250 mV to 450 mV across a resistive load having a resistance of 100 Ω. The midpoint of the differential output voltage is defined as the offset voltage and is required to be between 1125 mV and 1375 mV.
FIG. 1 shows a known differential output driver 80 that conforms to the LVDS standard and is described in the U.S. Pat. No. 6,111,431. In FIG. 1, mimicking circuit MC generates two reference voltages at nodes ND1 and ND6. The voltage at node ND1 is replicated in node ND2 using operational amplifier OPAMP1 and PMOS transistor P2 of the driver circuit DC. Operational amplifier OPAMP1 and transistor P2 together form a voltage buffer. Similarly, the voltage at node ND6 is replicated in node COM using operational amplifier OPAMP2 and NMOS transistor N1 of the driver circuit DC. Operational amplifier OPAMP2 and transistor N1 together form a voltage buffer. Transistors N21, N22, N23 and N24 form an H-bridge and are used as switches. Load resistor RL is connected between nodes A and B of the H-bridge. Since the input signals IN and INB are complements of each other, depending on the polarity of these input signals, current I2 flows from the H-bridge to transistor N1 either through the path defined by transistor N21, resistor RL, and transistor N24, or through the path defined by transistor N22, resistor RL, and transistor N23. The reference voltage levels are generated in MC such that when these voltages are replicated at nodes ND2 and COM, the resulting output voltage across resistor RL conforms to the LVDS standards.